Article View: comp.arch
Article #22590Re: Error in Posting of SPEC numbers on IBM systems
From: John Mashey
Date: Sat, 24 Feb 1990 02:53
Date: Sat, 24 Feb 1990 02:53
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1543 bytes
In article <AGLEW.90Feb22110902@oberon.csg.uiuc.edu> aglew@oberon.csg.uiuc.edu (Andy Glew) writes:
>I-caches get better hit rates than D-caches, but you quickly reach a
>point of diminishing returns - your I-cache hit rate is so good than
>improving it doesn't make too much difference to your performance.
>Moreover, if your memory system cycles comparable to your processor,
>but just has a large latency, then you can suck instructions out of
>memory, except for branches.
Note, also, that it also depends on the kind of programs you're
emphasizing. Systems that run lots of users, executing the kernel a lot,
or running big DBMs, have different characteristics than ones
aimed more at technical number crunch, especially of the
linear algebra type.
--
-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!brutus.cs.uiuc.edu!apple!vsi1!daver!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Error in Posting of SPEC numbers on IBM systems Message-ID: <36429@mips.mips.COM> Date: 24 Feb 90 02:53:04 GMT References: <36189@mips.mips.COM> <14900004@hpdmd48.HP.COM> <AGLEW.90Feb22110902@oberon.csg.uiuc.edu> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 18