🚀 go-pugleaf

In article <2134@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes:
>  Has anyone looked into an inline CPU package? Consider an extended
>SIPP concept, with the package being as long as needed, or even being
>several chips on a substrate. At 10 stations per inch, two sides, two
>levels, this gives 40 connections/inch. Obviously this could be pushed
>to at least double this, but by having a great long chip the congestion
>



High density IC packaging technologies are under development in all of the
major (and many minor) semiconductor manufacturers. What you are describing 
is basically a two-dimensional interconnect scheme. Texas instruments have
demonstrated this with actual DIE ! That is they have dice mounted vertically
on their edges on a substrate. The devices I've seen this demonstrated on were
memories but there's no reason why CPU-type dice couldn't be used.

In the UK, a company called Dowty developed a wierd thing called ``Chiprack''
which allowed stacks of little PCBs to be built up. The connections ran up th
outside of the stacks. This has been used to build demonstration Z80 and transputer
systems.

There are many more examples. In short, everyone would like interconnection
technologies which reduced the wiring delays in their systems and made things
cheaper and smaller.

However, the major pain with these schemes (and one of the reasons why they are
not in common use) is that it is difficult to get heat out of the assembly.
Most of the promising developments in this area use some kind of metal slug or
conduction path to get heat away from the dice.


I hope this sets your mind at rest that people are thinking about such things.

David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
Bristol,  England            |     (us): uunet!inmos.com!davidb
+44 454 616616 ex 547        | Internet: davidb@inmos.com