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Article #22646Re: BitBlt, new instructions for RISC.
From: Zachary T. Smith
Date: Tue, 27 Feb 1990 11:13
Date: Tue, 27 Feb 1990 11:13
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For all the engineering it would take (manhours) to get a given RISC processor to do 'fast' blitting, one might as well wait a few years until the (semiconductor) industry is capable of putting a blitter on a 1 megabit VRAM chip (or better yet on a 4 megabit chip), and then just do that. It'll get done eventually, so why come up with hacks in the meantime? -Zach Smith (zs04@andrew.cmu.edu) PS: Why wouldn't it get done? A blitter that operates on 1024 or 2048 bit lines per op and which can cache fonts in the DRAM as well would even a very fast blit processor running w/standard VRAM look like a toy.
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!pt.cs.cmu.edu!andrew.cmu.edu!zs04+ From: zs04+@andrew.cmu.edu (Zachary T. Smith) Newsgroups: comp.arch Subject: Re: BitBlt, new instructions for RISC. Message-ID: <AZua2yC00WB5Qqd2FJ@andrew.cmu.edu> Date: 27 Feb 90 11:13:02 GMT Organization: Carnegie Mellon, Pittsburgh, PA Lines: 14