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Article #22661Re: Cache Size
From: Dik T. Winter
Date: Wed, 28 Feb 1990 00:54
Date: Wed, 28 Feb 1990 00:54
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In article <8189@pt.cs.cmu.edu> koopman@a.gp.cs.cmu.edu (Philip Koopman) writes: > So, that's why most supercomputers seem to use vector register > files instead of caches for their vector units. > Well, no (depends on your definition of supercomputer of course; let us assume vector processor). There are systems without cache that use vector registers (Cray, NEC), or have memory to memory operations (Cyber 205). And there are processors with cache. Possibilities are: 1. No vector registers, bypass cache (Cyber 995). 2. Vector registers, bypass cache (i know none). 3. No vector registers, through cache (again, i know none). 4. Vector registers, through cache (IBM 3090, Convex, Alliant, Gould). So, no, vector registers are not a replacement for cache. -- dik t. winter, cwi, amsterdam, nederland dik@cwi.nl
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!mcsun!hp4nl!charon!dik From: dik@cwi.nl (Dik T. Winter) Newsgroups: comp.arch Subject: Re: Cache Size Keywords: garbage collection, locality of reference, cache size Message-ID: <8848@boring.cwi.nl> Date: 28 Feb 90 00:54:21 GMT References: <7393@pdn.paradyne.com> <76700146@p.cs.uiuc.edu> <1990Feb26.022057.28461@Neon.Stanford.EDU> <8189@pt.cs.cmu.edu> Sender: news@cwi.nl (The Daily Dross) Organization: CWI, Amsterdam Lines: 16