🚀 go-pugleaf

In article <438@peyote.cactus.org> woan@peyote.cactus.org (Ronald S. Woan) writes:
+In article <32344@shemp.CS.UCLA.EDU>, frazier@oahu.cs.ucla.edu (Greg Frazier) writes:
+> My understanding is that there are 3 ALU's, each with it's own
+> pipeline, and that is where the 5 ops/cycle peak is (i.e. 3 int
+> ops, 1 fp mult and 1 fp add).  Of course, you don't often get
+> more than 1 int opn at a time, as is revealed by the discrepancy
+> between the fp and int benchmarks.
+
+Where did this come from? From the simulator and talking to the designers,
+the three ALUs are the float add, float mult, and integer op units. If we
+could do (and schedule) multiple integer ops/cycle, you would be seeing
+some even more phenomenal benchmark results. I repeat 5 op/peak achieved
+by two branch instructions (counting these as integer ops these days?),
+float add-multiply instruction, and a single integer op.

I have since been informed that the two "other" int ALUs are
dedicated to cond. code generation and branch calculation,
respectively.  Oh, well, at least my source was correct about
the ALUs' existance, if not their operation.  Certainly, CC
generation and branch calculation would be counted as int ops,
since they *do* have to be executed one way or another on all
machines, they do require the ALU, and they are not fp.

+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
Greg Frazier				"Big A, little a / What begins with A?
frazier@CS.UCLA.EDU			Aunt Annie's Alligator / A ... a ... A"
!{ucbvax,rutgers}!ucla-cs!frazier			_Dr._Seuss's_ABCs_