Article View: comp.arch
Article #22694Re: IBM RISC System/6000 AS/400 (actually a diversion on the topic)
From: John R. Levine
Date: Wed, 28 Feb 1990 17:48
Date: Wed, 28 Feb 1990 17:48
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In article <1990Feb28.042949.21952@edm.uucp> geoff@edm.uucp (Geoff Coleman) writes:
> Actually this is about the first posting I've seen which
>mentions both the AS/400 and the 6000. ...
>It would seem to me that IBM just may have introduced an AS/400 killer.
From my understanding of the AS/400, based on some frustratingly vague
articles in the IBM Systems Journal last year, the AS/400 has a multi-level
virtual architecture. In particular AS/400 "executable" files are in fact
in a virtual microcode that is compiled to the native microcode at the time
the program is loaded. Different models of the AS/400 can and do have
different native microcodes. I see no reason why they couldn't use the 6000's
processor as such an engine, though to implement the AS/400's enormous
single level address space you'd probably want a different memory mapper
than the 801-like one that they use now.
--
John R. Levine, Segue Software, POB 349, Cambridge MA 02238, +1 617 864 9650
johnl@esegue.segue.boston.ma.us, {ima|lotus|spdcc}!esegue!johnl
"Now, we are all jelly doughnuts."
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!usc!snorkelwacker!spdcc!esegue!johnl From: johnl@esegue.segue.boston.ma.us (John R. Levine) Newsgroups: comp.arch Subject: Re: IBM RISC System/6000 AS/400 (actually a diversion on the topic) Message-ID: <1990Feb28.174838.7725@esegue.segue.boston.ma.us> Date: 28 Feb 90 17:48:38 GMT References: <20714@cfctech.cfc.com> <1990Feb28.042949.21952@edm.uucp> Reply-To: johnl@esegue.segue.boston.ma.us (John R. Levine) Organization: Segue Software, Cambridge MA Lines: 18