Article View: comp.arch
Article #22698Re: New instructions for RISCs (was Re: Byte ordering)
From: Colin Plumb
Date: Wed, 28 Feb 1990 23:51
Date: Wed, 28 Feb 1990 23:51
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In article <2377@castle.ed.ac.uk> aiadrmi@castle.ed.ac.uk (Alasdair Donald Robert McIntyre) writes: >torbenm@diku.dk (Torben [gidius Mogensen) writes: >> >>On the ARM2 (VL 86C010) and ARM3 processors from Acorn Computers / VLSI >>Technology, the load instruction can specify either a 12 bit signed constant >>shifted to anywhere in a 32 bit word or an address that can be indexed > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > correction - immediate constants *can-not* be shifted Well, you're sort of right... the standard 12-bit field is 8 bits of immediate data and 4 bits of rotate amount, which is multiplied by 2 before application. Thus, the ARM can form byte offsets from 0-255, word offsets from 0-1020, etc. -- -Colin
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!watserv1!watdragon!lion!ccplumb From: ccplumb@lion.waterloo.edu (Colin Plumb) Newsgroups: comp.arch Subject: Re: New instructions for RISCs (was Re: Byte ordering) Keywords: bitblt Message-ID: <21417@watdragon.waterloo.edu> Date: 28 Feb 90 23:51:18 GMT References: <7345@pdn.paradyne.com> <168@zds-ux.UUCP> <7366@pdn.paradyne.com> <1990Feb10.154033.4271@mentor.com> <1990Feb19.130019.2833@diku.dk> <2377@castle.ed.ac.uk> Sender: daemon@watdragon.waterloo.edu Reply-To: ccplumb@lion.waterloo.edu (Colin Plumb) Organization: U. of Waterloo, Ontario Lines: 16