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Article #22723

Re: 64-bit addresses

#22723
From: Anand Iyengar
Date: Sun, 18 Feb 1990 04:21
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In article <29718@brunix.UUCP> phg@cs.brown.edu (Peter H. Golde) writes:
>One might note that implementing a 64-bit address space
>with 64 KB pages and 8 bytes/page in the page table requires
>2 billion megabytes of page-table space.  Hmmmmm.....
	This is for the final level of the translation, and it need not be
fully resident (!).  With each successive (K step) indirection you'd add
2^(64 - 13*k) { 1 <= K <= 4 } bytes in page tables.  Only the highest
level (lowest K) need be loaded.  However, you do buy the space with time
(successive look-ups).  

	What's the general feeling on future page sizes (I'm guessing that
64K was picked here to make the page-tables smaller)?  Is it reasonable
to assume that they are going to increase also (as bandwidth/latency
increases), or will we lose more by making pages larger?  

							Anand.  

--
"Surely you're not happy, you no longer play the game..."
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From: iyengar@grad2.cis.upenn.edu (Anand Iyengar)
Newsgroups: comp.arch
Subject: Re: 64-bit addresses
Message-ID: <20534@netnews.upenn.edu>
Date: 18 Feb 90 04:21:44 GMT
References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <11112@encore.Encore.COM> <753@dgis.dtic.dla.mil> <WAYNE.90Feb11165528@dsndata.uucp> <3606@uceng.UC.EDU> <757@dgis.dtic.dla.mil> <4852@scolex.sco.COM> <29718@brunix.UUCP>
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Reply-To: iyengar@grad2.cis.upenn.edu.UUCP (Anand Iyengar)
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