🚀 go-pugleaf

In article <21417@watdragon.waterloo.edu> ccplumb@lion.waterloo.edu (Colin Plumb) writes:
>In article <2377@castle.ed.ac.uk> aiadrmi@castle.ed.ac.uk (Alasdair Donald Robert McIntyre) writes:
>>torbenm@diku.dk (Torben [gidius Mogensen) writes:
>>>
>>>On the ARM2 (VL 86C010) and ARM3 processors from Acorn Computers / VLSI
>>>Technology, the load instruction can specify either a 12 bit signed constant
>>>shifted to anywhere in a 32 bit word or an address that can be indexed
>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>
>> correction - immediate constants *can-not* be shifted
>
>Well, you're sort of right... the standard 12-bit field is 8 bits of immediate
>data and 4 bits of rotate amount, which is multiplied by 2 before application.
>Thus, the ARM can form byte offsets from 0-255, word offsets from 0-1020,
>etc.
>-- 
>	-Colin

Chaps, please, you're both both right and wrong:

The immediate field in Data Processing instructions (ADD, ORR, AND,
MOV, CMP etc.) *IS*
>			the standard 12-bit field of 8 bits of immediate
>data and 4 bits of rotate amount, which is multiplied by 2 before application.
Thus you can make 0-255, 256-1020 4-tuples, 1024-4080 16-tuples etc.
etc., including nice numbers like 0xFC000003, 0x0030C000, etc.
	MOV	R0, #0x00034400		; get a number
	ANDS	R0, R1, #0x83000000	; test some flag bits.
	TEQP	PC, #0xFC000002		; select processor mode 2
	ADD	R2, R2, R2, ASL #4	; R2 *= 17
	RSB	R3, R2, R3, ASR #1	; R3 = R3/2 - R2
	AND	R4, R5, R6, ASL R7	; R4 = R5 + R6 << R7
and other shifts by constants (0-31/1-32) or registers here too!

The immediate field in Data Transfer (LDR[B],STR[B]) instructions is a
12 bit *unsigned* number, which can be added to OR subtracted from the
base register depending on another bit entirely in the instruction.
So if you like it's a *13* bit signed number.  It is not shifted at
all.  Ever.
	LDR	R0, [ R1, #4092 ] 	; get a word from far away
	LDRB	R2, [ R3, #4095 ] 	; get a byte from far away
	LDRB	R4, [ R5, -#4095 ]	; get a byte from far backwards
Also
	LDRB	R6, [ R7, R8 ]		; get ((char *)R7)[R8]
	LDR	R9, [ R10, R11 ASL #4 ] ; get ((int *)R10)[R11]
and other shifts by constants (0-31/1-32) here too!

Note that offsets for a word transfer *are* byte resolution; it's just
that non-word aligned word transfers give undefined (well, consistent,
definable, but not guaranteed not to change from one ARM revision to
another; usual thing) answers on current ARMs.

	- Huge

BTW, I posted the truth about this earlier under "Re: New instructions
for RISCs" or whatever that thread was called.

DISCLAIMER: if there's a typo or lie here blame me, not Acorn, I speak
only for myself, etc.