🚀 go-pugleaf

In article <203@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
in reply to 
alan@oz.paradyne.com (Alan Lovejoy) and  Benjamin Chase <bbc@rice.edu>

>I can think of a simpler way to do this, with an instruction just like load
>except it doesn't wait for the memory operation to complete or write a
>register, its only effect would be to do a read to fill the cache line.  

Yes indeed.  That's just what Ben suggested.  I call it cache prefetching
and he called it "whispering gently in the processor's ear", but it
seems like a good idea either way.

Of course, we want the cache miss handling to occur asynchronously with
normal processing.  That is, don't freeze the processor just because there's
a reload happening.

>Of course if my interpretation is correct, the 88k
>can accomplish almost the same thing with its scoreboard; the compiler just
>move the load itself up.  The only difference is when the register gets
>allocated.

Right, assuming cache misses are handled like I want.
Of course, we suddenly see a need for lots of registers.
--
Preston Briggs				looking for the great leap forward
preston@titan.rice.edu