Floating Point Multipliers

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Article #22767

#22767

From: Dr. Ranga R. Vemuri
Date: Sun, 04 Mar 1990 06:52

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Does any one have pointers to info. on floating point arithmetic units
(multipliers and dividers in particular) implemented in CMOS or
NMOS.  I  am particularly looking for information on single chip 
implementations and their performance (area, speed etc...).

- Ranga.


-- 
Dr. Ranga Vemuri                                     ranga@uceng.uc.edu
Laboratory for Digital Design Environments           (513)-556-4784
M.L. 30, Dept. Electrical & Computer Engineering     (513)-556-4769  
University of Cincinnati, Cincinnati, OH 45221, USA

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!mailrus!iuvax!uceng!ranga
From: ranga@uceng.UC.EDU (Dr. Ranga R. Vemuri)
Newsgroups: comp.arch,comp.lsi
Subject: Floating Point Multipliers
Message-ID: <3880@uceng.UC.EDU>
Date: 4 Mar 90 06:52:11 GMT
Followup-To: ranga@uceng.uc.edu
Organization: College of Engg., Univ. of Cincinnati
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