🚀 go-pugleaf

           
    Just When You Thought It Was Safe to Go on Vacation ....

                                 HOT CHIPS II                        
                      A Symposium on High Performance Chips 
                                ADVANCE PROGRAM

                Santa Clara University, Santa Clara, California
                              August 20-21, 1990

               Sponsored by the Technical Committee on Microprocessors
                  and Microcomputers of the IEEE Computer Society



           General Chairman:       Hasan Alkhatib, Santa Clara University
           Program Co-Chairman:    Alan Jay Smith, U. C. Berkeley
           Program Co-Chairman:    John Crawford, Intel
             
           Organizing Committee: 

                 Martin Freeman, Philips Research, Vice Chair TCMM
                 Andy Goforth, NASA Ames Research Center, Publicity
                 Jack Grimes, Mass Microsystems, Past Program Chair
                 Glen Langdon, U. C. Santa Cruz, Chair TCMM
                 Nam Ling, Santa Clara University, Registration
                 Doug Marquardt, Santa Clara University, Arrangements
                 Stacy Pena, CrossCheck Technology, Publicity
                 Robert Stewart, Stewart Research, Treasurer
                 Cynthia Wirtz, CrossCheck Technology, Publications
          
           Program Committee:
  
                       Forest Baskett, Silicon Graphics
                       David Ditzel, Sun Microsystems
                       John Hennessy, Stanford University
                       Teresa Meng, Stanford University
                       David Patterson, U. C. Berkeley
                       Mario Tokoro, Keio University         



    Monday, August 20

        8:00- 8:30   On-site Registration: Mayer Theater
        8:30- 9:00   Welcome & Opening Remarks: Hasan Alkhatib, Alan Jay Smith, 
                     John Crawford
        9:00-10:30   Session I: High Performance Processors I
                        GaAs SPARC RISC Processor, Gary McMillian, Systems & 
                           Processes Eng. Corp.
                        The SPARC Lightning Processor, Bruce Lightner, Metaflow 
                           Technology
                        The MIPS R/6000 Microprocessor, George Taylor, MIPS 
                           Computer Systems

       10:30-10:45   BREAK

       10:45-12:15   Session II: Performance and Caches
                        The SPEC and Perfect Club Benchmarks: Promises and 
                           Limitations, Rafael Saavedra-Barrera, U. C. Berkeley
                        Performance Characteristics of the i960CA Superscalar 
                           Microprocessor, Steve McGeady, Intel
                        High Integration Second Level Cache for the i486 CPU
                           Adi Golbert, Intel 

       12:15- 1:45   LUNCH

        1:45- 3:15   Session III: Video & Graphics
                        A Video Compression Chip Set, Peter Ruetz, LSI Logic
                        C_Cube CL550 Image Coprocessor, Steven Purcell, C_Cube 
                           Corp
                        DVI and i750 Chip Set, Sanjay Vinekar, Intel
                        
        3:15- 3:30   BREAK

        3:30- 4:30   Session IV: Packaging
                        Dense Stack, Floyd Eide, Dense-Pak Microsystems
                        Silicon Multichip Modules, Kamran Malik, nChip 

        4:30- 5:50   Session V: Floating Point
                        A 120 MFLOP CMOS Floating Point Unit, Alan Quek, Weitek
                        A 100 MHz Floating Point/Integer Processor, 
                           Gregory Taylor, BIT

        6:30-        BANQUET. Banquet Speaker: John Doerr, General Partner, 
                        Kleiner Perkins Caufield & Byers.
                        

    Tuesday, August 21

        8:00- 8:30   On-site Registration: Mayer Theater
        8:30-10:30   Session VI: High Performance Microprocessors II
                        96-bit General Purpose IEEE Floating Point Dual Port 
                           Processor, Terry Schultz, Motorola
                        A Single Chip Integer VLIW Processor Core, 
                           Gerrit Slavenburg, Philips Research
                        The Clipper Super Scalar CMOS Chip Set, Howard Sachs,
                           Intergraph  
                        Experience with the i860 CPU, John Casey, 
                           Hauppauge Corp

       10:30-10:45   BREAK

       10:45-12:15   Session VII: Systolic Arrays
                        Touchstone DELTA Prototype: A 30 Gigaflop Scalable 
                           Parallel Computer, Justin Rattner, Intel
                        100 MOP LIW Microprocessor for Multicomputers
                           Craig Peterson, Intel
                        Datawave - A Data Driven Video Signal Array Processor
                           Ulrich Schmidt, ITT

       12:15- 1:45   LUNCH

        1:45- 3:45   Session VIII: Routing and Interconnect
                     Caltech Mesh-Routing Chips
                        Charles Seitz, Caltech
                     Get Off the Bus and Call a Taxi
                        Paul Scott, AMD
                     Hod Rod: 1 Gbit/Sec Data Communications
                        Jonathan Zierk, Gazelle

        3:45- 4:00   BREAK

        4:00- 5:30   Session IX: IBM RS/6000
                     IBM RS/6000 Overview and Performance
                     Compiling for the RISC System/6000 Branch Unit
                        Martin Hopkins, IBM Watson Research 
                     IBM RS/6000 Floating Point Architecture and 
                        Implementation

        5:30         CLOSING REMARKS




 ______________________________________________________________________________                 
                           
                          Registration Form: Hot Chips II
                       Santa Clara University, Santa Clara, CA 
                                August 20-21, 1990

           Make Checks Drawn on US Bank Payable to: Hot Chips Symposium
           Mail this completed form with payment to:

                                  Nam Ling
                                  Department of EECS
                                  Santa Clara University
                                  Santa Clara, CA 95053
                                  (408)-554-4794



 Name_________________________________________________________________________

 Organization_________________________________________________________________
  
 Address______________________________________________________________________

 City, State, ZIP_____________________________________________________________

 Telephone Number_____________________________________________________________

 FAX Number___________________________________________________________________

 Member of (Circle One)             IEEE                  ACM

 Membership Number____________________________________________________________
 
 Charge to (Circle One)             VISA                  MASTERCARD

 Card Number__________________________________________________________________

 Expiration Date______________________________________________________________

 Signature____________________________________________________________________




 REGISTRATION FEES:

                          Postmarked by July 23      Subsequent Registration

 IEEE/CS or ACM Member             $150                       $230

 Non-Member                        $230                       $280
                                                           
 IEEE Student Member               $50                        $75 

                     
 Symposium registration includes attendance, one copy of notes, two luncheons, 
 coffee breaks, Sunday reception, and Monday evening banquet. Registration may 
 be charged to VISA or MASTERCARD. Registration charged to credit cards may be 
 faxed to Nam Ling at (408)-554-5474. On-site registration is available Sunday 
 evening at the reception, and every morning at the Symposium.

 Reception: 5-7 PM, Sunday, August 19, Benson Parlors' Patio, Santa Clara 
 University Campus.  

 The 1989 Hot Chips Symposium was a huge success, and prompted articles in two 
 special issues of IEEE Micro magazine. This year's Hot Chips II will again 
 bring you the latest developments in chip technology used to construct 
 high-performance workstations and systems.  
 
 FOR MORE INFORMATION CONTACT:  goforth@pluto.arc.nasa.gov