🚀 go-pugleaf

"Jeffrey S. Dutky" <dutky@bellatlantic.net> writes:

>The problem with building very large associative memories is that
>most of your silicon goes into building comparitors. Essentially,
>you are building one huge parallel processor that only has one
>instruction (compare A to all registers, return register that
>matches). This is VERY watefull of silicon and gets pretty slow
>as the number of "registers" to compare to gets large. This is
>why you almost never see caches with anything more that 4-way
>associativity, the higher associativity is EXPENSIVE (both in
>money and in speed) and doesn't get you very much in terms of
>improving cache hit rate.

Hmm. ARM3 and ARM610 use 64-way associative caches and StrongARM uses
32-way associative caches. Since price has been an important
consideration in the design of these, I can't imagine that the choice
of 64-way associativity has been very costly compared to e.g 4-way
associativity. Or maybe the designers felt that the high associativity
was important enough to warrant the price, maybe because these
processors don't have 2nd level caches.

	Torben Mogensen (torbenm@diku.dk)