Article View: comp.arch
Article #23004Cache design for VLIW arch.
From: Han Kyung Nam
Date: Thu, 10 Oct 1996 00:00
Date: Thu, 10 Oct 1996 00:00
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1151 bytes
like superscalar, VLIW can execute more instructions in one cycle. but, if external instruction bus width is 32 bits (= 1 instruction width), then I think there will be so many miss penalties than uni-processor's when cache miss occurs. so, how can I solve this problem for better optimized performance? And, I've heard there are many processors using VLIW arch in the world, one example is Philips' TriMedia DSP chip that uses 16K VLIW instruction cache. but it's not easy to find papers or books that mentions this cache. can you help me find these things? Thank you...
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 1133f6,e654f766864c0877,start X-Google-Attributes: gid1133f6,public X-Google-Thread: 102b75,e654f766864c0877,start X-Google-Attributes: gid102b75,public X-Google-Thread: f8fcc,e654f766864c0877,start X-Google-Attributes: gidf8fcc,public From: "Han Kyung Nam" <paganini@vlsi5.kaist.ac.kr> Subject: Cache design for VLIW arch. Date: 1996/10/10 Message-ID: <01bbb648$e1e67ce0$ebe6f88f@lsipc5.kaist.ac.kr> X-Deja-AN: 188363611 organization: KAIST EE newsgroups: comp.arch,comp.dsp,fj.comp.dsp