🚀 go-pugleaf

Hi folks,

As a part of a larger project, I have developed a C++ to netlist
compiler. The main goal is to be able to emulate the generated
hardware by compiling the source code with a regular C++ compiler.
The targeted hardware is mainly FPGA chips.

I actually compiled code all the way into Xilinx chips. And they
run. I think this compiler might be of some interest to other
researchers, so I decided to make it freely available under a GPL type
of licensing.

At the current time, the compiler:
  - is written in C++. Can be compiled by g++ 2.6.3.
  - needs the LEDA 3.1 library (available by anonymous ftp).
  - will directly generate ViewLogic WIR files and the associated
    symbols. It should be easy to add some code to have it generate
    netlists of different format.

The target (FPGA) architecture is described directly in the source
code, preferably in an included file. Thus it should be extremely easy
to generate netlists for different FPGA architectures. A partial
description of the XC4000 family is provided in the sources.

This is still beta quality code. The documentation is very sparse.

How to get it:
  ftp://lslsun5.epfl.ch/pub/nlc-0.6.tar.gz
then look at the README file for terse explanations on how to build...

I'll also put a compiled binary version for sparc, Solaris 2.3 (sorry,
this is all I have access to...)

There is a Majordomo mailing list for discussion about nlc. To be
added to the list, send a message containing the line
subscribe nlc
to majordomo@lslsun.epfl.ch. The subject is irrelevant.

If some folk manage to compile nlc for some other platform, they can upload
the binary on lslsun5 and tell the list...

Take care,
					Christian Iseli
--

					Christian Iseli
					LSL-DI-EPFL
					Lausanne, Switzerland