🚀 go-pugleaf

Factory wrote in message ...
>In article <7bjr4a$cq2$1@nnrp1.dejanews.com>, aa158@valleynet.on.ca
>says...
>> "The Playstation 2's CPU, jointly developed by Toshiba and SCE, is an
enhanced
>> version of the device described at ISSCC. The device has floating-point
>> performance of 6.2 Gflops..."
>> "Intel said Merced would achieve 3-Gflops extended-precision
floating-point
>> performance and 6-Gflops single-precision performance."
>
>  Hmm I don't know about the merced, but from the specs I saw for the
>psx2 system, it has less registers (erm from what I remember 32 general
>regs, I assume the fp regs are similar), vs. the merced's 128 regs set
>(if I remember rightly).
>  The caching on the psx2 was fairly unimpressive too, it had a 8k/16k
>instruction/data cache and 16k scratchpad mem, no mention was made of any
>other forms of caching. Considering that the current low end pentium
>class chips have much more caching, I do not doubt that the merced
>processors will have better caching.
>  If those specs are roughly right (I'm doing this from memory..) I would
>expect the merced to out perform the psx2's cpu in real world work.
>
>  Actually from looking at the specs of the psx2 I would guess that the
>complete system will perform as well as a tnt equipped celeron 400, but
>that is just a guess.

The Cpu sounds pretty yummy alone...
    Emotion Engine Features and General Specifications
    CPU core 128bit RISC (MIPS IV-subset)
    Clock Frequency 300MHz
    Integer Unit 64bit (2-way Superscalar)
    Multimedia extended instructions 107 instructions at 128bit width
    Integer General Purpose Register 32 at 128 bit width
    TLB 48 double entries
    Instruction Cache 16KB (2-way)
    Data Cache 8KB (2-way)
    Scratch Pad RAM 16KB (Dual port)
    Main Memory 32MB (Direct RDRAM 2ch@800MHz)
    Memory bandwidth 3.2GB/sec
    DMA 10 channels
    Co-processor1 FPU (FMAC x 1, FDIV x 1)
    Co-processor2 VU0 (FMAC x 4, FDIV x 1)
    Vector Processing Unit VU1 (FMAC x 5, FDIV x 2)
    Floating Point Performance 6.2GFLOPS
    Geometry
    + Perspective Transformation 66Million Polygons/sec
    + Lighting 38Million Polygons/sec
    + Fog 36Million Polygons/sec
    Curved Surface Generation (Bezier) 16Million Polygons/sec
    Image Processing Unit MPEG2 Macroblock Layer Decoder
    Image Processing Performance 150Million Pixels/sec
    Gate width 0.18 micron
    VDD Voltage 1.8 V
    Power Consumption 15 Watts
    Metal Layers 4
    Total Transistors 10.5 Million
    Die Size 240 mm2
    Package 540pin PBGA

But then the GP makes you go oooooooooohhhhhhhhhhhhh
    Graphics Synthesizer � Features and General Specifications
    GS Core Parallel Rendering Processor with embedded DRAM
    Clock Frequency 150 MHz
    No. of Pixel Engines 16 (in Parallel)
    Embedded DRAM 4 MB of multi-port DRAM (Synced at 150MHz)
    Total Memory Bandwidth 48 Giga Bytes per Second
    Combined Internal
    Data Bus bandwidth 2560 bit
    Read 1024 bit
    Write 1024 bit
    Texture 512 bit
    Display Color Depth 32 bit (RGBA: 8 bits each)
    Z Buffering 32 bit
    Rendering Functions Texture Mapping, Bump Mapping
    Fogging, Alpha Blending
    Bi- and Tri-Linear Filtering
    MIPMAP, Anti-aliasing
    Multi-pass Rendering
    Rendering Performance
    Pixel Fill Rate 2.4 Giga Pixel per Second
    (with Z buffer and Alphablend enabled)
    1.2 Giga Pixel per Second
    (with Z buffer, Alpha and Texture)
    Particle Drawing Rate 150 Million /sec
    Polygon Drawing Rate 75 Million /sec (small polygon)
    50 Million /sec (48 Pixel quad with Z and A)
    30 Million /sec (50 Pixel triangle with Z and A)
    25 Million /sec (48 Pixel quad with Z, A and T)
    Sprite Drawing Rate 18.75 Million (8 x 8 Pixels)
    Display output NTSC/PAL
    Digital TV (DTV)
    VESA (maximum 1280 x 1024 pixels)
    Silicon process technology 0.25 � 4-level metal
    Total number of transistors 43 Million
    Die size 279mm2
    Package Type: 384 pin BGA


mmmmm