Article View: comp.arch
Article #2352Need info on SPARC & MIPS
From: S. Storkel
Date: Wed, 27 Sep 1989 20:55
Date: Wed, 27 Sep 1989 20:55
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1147 bytes
I need some pointers to information on the SPARC and MIPS reduced
instruction set processors. I am mainly interested in the architecture
of these chips. Things like pipelines, instruction formats,
instruction types, exceptions, interrupt handling, data
representation, etc. I have access to Sun's SPARC Architecture Manual
and RISC Tutorial, but I'm looking for more detailed information on
the actual implementation.
If anybody could help me out here, I really appreciate it. Please
reply to:
storkel@rice.edu ...!{uunet, sun}!rice!storkel
if possible. Thanks for the help.
-- Scott Storkel
Disclaimer: Any views expressed here DO NOT represent the opinions of
Shell Development Company, BLUware, or Rice University.
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!wuarchive!mailrus!bcm!shell!storkel From: storkel@limpet.shell.com (S. Storkel) Newsgroups: comp.arch Subject: Need info on SPARC & MIPS Message-ID: <STORKEL.89Sep27155536@limpet.shell.com> Date: 27 Sep 89 20:55:36 GMT Sender: usenet@shell.com Distribution: na Organization: Shell Development Company, Bellaire Research Center, Houston, TX Lines: 24