🚀 go-pugleaf

In article <15904@dartvax.Dartmouth.EDU> jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin) writes:
>
>So...my question:  most (all?) of the current RISC processors
>(29000, 88000, 80860, etc) include pipeline interlock logic.

  MIPSco and SPARC also

At Hot Chips, John M. mentioned interlocks as one of the nice features
of the MIPSco chips.

>Could someone familiar with these processors comment on the
>implications of this decision:
>
>    -- How much of the total chip area is occupied by
>       pipeline interlock logic?

Not much. 

>
>    -- If the interlock logic were eliminated, could the 
>       processor cycle time be decreased?  By how much?

In general, very little if at all. My drinking buddies who are hw
jocks think they know how to do such things in parallel with real
work. :>
> 
>    -- How long (in person-weeks/years, whatever) did it take
>       to design the interlock logic?  

Dunno. Certainly seems unlikely to anywhere near as costly as the
software havoc not having interlocks costs. Aside from the compiler
development, inevitable bugs introduced by hand coders and the like,
is the fact that your binaries simply won't run on the next generation
device (unless you really constrain the hw jocks). 

Upgrading your machine --> all new software is unpopular. Sufficiently
so that it seems that few if any commerical designs will completely
skip interlocks.

>
>
> 
>   **  Jeff Kuskin,  Dartmouth College
> 
>   **  E-Mail:  jskuskin@eleazar.dartmouth.edu


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