🚀 go-pugleaf

In article <269@ssp1.idca.tds.philips.nl> roelof@idca.tds.PHILIPS.nl (R. Vuurboom) writes:
>When (precisely :-) is an exception imprecise? 

When the state it saves doesn't reflect the true machine state.  Typically
this is because some of the instructions before the one pointed to by the
exception program counter haven't been completed, or some subsequent ones
have.  If you're lucky, there will be some secret registers or something
that allow you to patch up the machine state, if you're unlucky you're, well,
out of luck.

Imprecise interruptions are more common on heavily pipelined processors
where there are a lot of operations in progress at once.  They can be
avoided if the designer is willing to put in sufficient hardware to be able
to back out or annul everything in the pipeline after the interrupting
instruction, but the extra complexity and performance hit can be great.

The classic imprecise interrupter, the 360/91, would give you a semi-random
instruction address near the interrupting instruction (or perhaps far, far
away from it if it had decoded an unconditional branch or two in the
meantime) and there was no way to recover the machine state.  It aborted
your job with a system 0C0 code, known as S0C0 pronounced "socko."  Since
most floating point exceptions such as divide by zero or overflow were
imprecise, we got socko-ed a lot.
-- 
John R. Levine, Segue Software, POB 349, Cambridge MA 02238, +1 617 492 3869
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