🚀 go-pugleaf

In article <1068@m3.mfci.UUCP> cutler@mfci.UUCP (Ben Cutler) writes:
*** some deleted ***
>VLIWs and Trace Scheduling (TM) Compiler technology go hand-in-hand.  Ellis
>describes why the FPS-164 doesn't qualify as a good compilation target in
>his thesis:

I guess what I find strange is that the definition of a type of computers
and a (trademarked) compiler technology are so closely tied.  The definition
doesn't seem as general as the RISC and CISC definitions (which I won't
attempt to give here).  It is strange that the definition doesn't encompass
the similarities with the FPS architecture.

Ex-FPS persons I know, immediately saw the similarities with the
Multiflow and correctly anticipated (in a general way) how it would
perform.  We would have welcomed the improvements in register unit
bandwidth that Ellis requires, though we would not have given up
the ability to latch the result of one pipeline directly to the
input of another, if there were a performance penalty.  A sophisticated
compiler technology should be able to handle this (but why bother
if you don't have to?).  From a marketing viewpoint the virtual
memory and multiuser OS were more important features.  The Multiflow
architecture just seemed a natural evolution of the FPS architecture.

From your posting, it appears Ellis correctly understood the limitations
of the FPS architecture and his analysis of it seems to acknowledge
some related place for it in history.

*** much deleted ***

>If you want to know more, then read the thesis, which is extremely
>well-written and informative.

Yes, I hope to have the opportunity to read this.
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