Article View: comp.arch
Article #2580Re: test and set facility
From: James Shankland
Date: Sat, 14 Oct 1989 17:37
Date: Sat, 14 Oct 1989 17:37
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1496 bytes
In article <29463@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >In article <200@rangkom.MY> napi@rangkom.MY (Mohd Hanafiah b. Abdullah) writes: >>[How do you do atomic test and set on MIPS?] > $ From: jeffd@norge.sgi.com (Jeff Doughty) > $ Subject: Re: atomic instructions on R2000 > $ Date: 3 Oct 89 15:24:39 GMT > > ... > $ [By using a private bus and external gate-array per processor.] > $ The gate-array is actually a bus-watching cache that maintains the > $ state of 64K spinlocks.... That's pretty interesting. But there's another aspect to the original question: how do you do atomic test-and-set on a uniprocessor MIPS system, without atomicity being broken by preemption? In kernel mode, presumably you can always disable interrupts, do the test, do the set, and re-enable interrupts. But what about in user mode? It's awfully handy if user processes sharing memory can do atomic t&s without a kernel call .... jas
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arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!tut.cis.ohio-state.edu!ucbvax!pasteur!postgres!jasReferences:
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!tut.cis.ohio-state.edu!ucbvax!pasteur!postgres!jas From: jas@postgres.uucp (James Shankland) Newsgroups: comp.arch Subject: Re: test and set facility Keywords: MIPS Message-ID: <18381@pasteur.Berkeley.EDU> Date: 14 Oct 89 17:37:04 GMT References: <200@rangkom.MY> <29463@obiwan.mips.COM> Sender: news@pasteur.Berkeley.EDU Reply-To: jas@postgres.berkeley.edu (Jim Shankland) Organization: The Eddie Group Lines: 22