🚀 go-pugleaf

In article <MCCALPIN.89Oct16141656@masig3.ocean.fsu.edu> mccalpin@masig3.ocean.fsu.edu (John D. McCalpin) writes:
>The larger chip vendors are paying more attention to parallelism now,
>but it appears to be in the context of 2-4 processor parallelism.  It
>is not likely to be possible to make these chips work together in
>configurations of 1000's with the application of "glue" chips....
These microprocessors, for the most part, are being designed to work in
a small processor count coherent cache shared memory environment.  This
is the reason why examining scalable coherent cache systems is so imporant.
The same micros, with their capability to lock a cache line for a while
to do an indivisible op, will work fine in the scalable systems.
I agree that they won't be optimal, but they will be within 90% of optimal
and that is all that is required.  The MAJOR problem with current micros
in a scalable shared memory environment is their 32 bit addressing.
Unfortunately, no 4 processor system will ever need more than 32 bit
addresses, so we will have to BEG the micro vendors to put in bigger
pointer support..

>This is not to mention the fact that software technology for these
>parallel supercomputers is depressingly immature.  I think traditional
>moderately parallel machines (e.g. Cray Y/MP-8) will be able to handle
>existing scientific workloads better than 1000-processor parallel
>machines for quite some time....
The software question is the really hary one, that is why LLNL is
sponsoring the Massively Parallel Computing Initiative.  We see
scalable machines being very cost effective and are making a substantial
effort in the application software area.



brooks@maddog.llnl.gov, brooks@maddog.uucp