🚀 go-pugleaf

In article <16190@vail.ICO.ISC.COM> rcd@ico.ISC.COM (Dick Dunn) writes:
>This week's EE Times features a front-page article about IBM's forthcoming
>line of RISC machines based on the `America' processor, presented at ICCD.
>The article mentions that the architecture has 184 instructions!...

>	...ERISC - Extended Reduced Instruction Set Computer
>as in "our machine has more fewer instructions than yours doesn't."
>

Believe it or not, the presenters DID redefine RISC!  The now say that
it stands for "Reduced Instruction Set Cycles"!  So much for a convergence
of the meaning of a too-nebulous term.

What amazed me about this architecture more than the number of instructions
was the anti-RISC approach to some of its elements.  The most glaring ex-
ample IMHO is the fact that its floating point processor implements register
renaming in HARDWARE!  There is nothing wrong with that in and of itself,
but it is something that is almost trivially implemented in a compiler and
therefore the RISC philosophers tell you to PUT it in the compiler.

I believe that the only reason that the term RISC is associated with this
architecture is for the marketing mileage that it gives them.  Perhaps
their efforts to redefine term are a token effort to assuage the confusion
of those that can see through this somewhat blatant marketing ploy.

>It would be interesting to know what the machine really looks like...

A reasonable description of most of the architecture appears in the papers
presented there -- the transactions are available.

Rick Miller
11012 Howland Drive
Reston, VA

The opinions expressed here are my own.

Please reply to rmiller@gmuvax2.gmu.edu