Re: 1Meg DRAM supply voltage

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Article #2691

#2691

From: Henry Spencer
Date: Thu, 19 Oct 1989 16:37

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In article <1T9NpG#464lr4=eric@snark.uu.net> eric@snark.uu.net (Eric S. Raymond) writes:
>> (One of the gems of my collection is an unintentionally-hilarious paper
>> from an IEEE conference proceedings that proves, in some detail, that it
>> is impossible to build 64Kb DRAMs with optical lithography.)
>
>O.K., now please tell us which limiting assumption went wrong and why.

Hey, I'm a systems programmer, not a chip designer -- *I* don't know! :-)

If enough people are interested, I can dig out the paper and post the gist
of the argument, so the real chippies :-) can pick holes in it.
-- 
A bit of tolerance is worth a  |     Henry Spencer at U of Toronto Zoology
megabyte of flaming.           | uunet!attcan!utzoo!henry henry@zoo.toronto.edu

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Message-ID: <1989Oct19.163734.20976@utzoo.uucp>

Path: arc1-ca.pugleaf.net!utzoo!henry

References: <6797@hubcap.clemson.edu> <1989Oct17.154651.16073@utzoo.uucp> <1T9NpG#464lr4=eric@snark.uu.net>

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Newsgroups: comp.arch
Path: arc1-ca.pugleaf.net!utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: 1Meg DRAM supply voltage
Message-ID: <1989Oct19.163734.20976@utzoo.uucp>
Organization: U of Toronto Zoology
References: <6797@hubcap.clemson.edu> <1989Oct17.154651.16073@utzoo.uucp> <1T9NpG#464lr4=eric@snark.uu.net>
Date: Thu, 19 Oct 89 16:37:34 GMT

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