🚀 go-pugleaf

In article <2450@odeon.ahse.cdc.com> bga@odeon.ahse.cdc.com (Bruce Albrecht) writes:
>In article <35979@lll-winken.LLNL.GOV>, brooks@vette.llnl.gov (Eugene Brooks) writes:
>> Unfortunately, no 4 processor system will ever need more than 32 bit
>> addresses, so we will have to BEG the micro vendors to put in bigger
>> pointer support..
>
>Oh really?  CDC has several customers that have databases that exceed 2**32 
>bytes.  Our file organization considers files to be virtual memory segments.
>We already need pointers larger than 32 bits.  IBM's AS400 has a virtual
>address space greater than 32 bits, too.  If the micro venders don't see a
>need for it, they're not paying attention to what the mainframes are really
>providing for their very large system customers.

In 1947, John Von Neumann anticipated that 4K word of 40 bits each was enough
for contemporary problems and so the majority of machines then had that much
RAM (or what passed for it in the technology of the day).  This is ~2**12
bytes worth of usefulness in todays thinking (though not in bits). Over the
next 40 years we've grown to the point where 2**32 bytes is a common theoretical
limit for machines with a large number of machines in the 2**30 bytes is
fairly common.  This translates into 18-20 bits of address over 40 years.
Or, 1 bit of address every 2 years or so.

Given the trend to having micro architectures last 5 to 8 years, this means
that a micro architecture should have atleast 4 additional address lines
at its announce or 5 additional when its development is started.

In the PC space, 16 megabytes seems to be the common upper limit.  Any PC
therefore should have not 2**24 as a limit but 2**26 at the minimum.

IMHO, at least :-)

Robert Cousins
Dept. Mgr, Workstation Dev't.
Data General Corp.

Speaking for myself alone.