🚀 go-pugleaf

In article <1989Oct19.155752.13028@mentor.com> geraldp@mentor.com (Gerald Page) writes:
   >>
   >>According to the text "Computer Architecture, a Modern Synthesis", 
   >>by Subrata Dasgupta, John Wiley & Sons, 1989, most RISC processors
   >>have the following 6 characteristics:

     ...

   >>2.  All instructions (operations) consume a single processor cycle
   >>    with the possible exceptions of LOAD and STORE.

Durn, the R3000 isn't RISC then.  Integer divide (the single instruction
"div" which divides 32b operands) takes 33 cycles, and integer
multiply ("mul") takes 12.  And heck, good ole SPARC and HP Precision
and Clipper & i860 & i960 & Moto 88K & GE RPM-40 *all* have floating
point instructions that "consume more than a single processor cycle".

Acorn, you've got the RISC market all to yourself.

     ...

   >>5.  The use of hardwired rather than microcoded control.

But this precludes Clipper and the i960.
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After seeing this, I am curious to know, how much $ does Dasgupta
want for his book, anyway??
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}