🚀 go-pugleaf

 
For a "well designed" computer, how many gate delays are there in one
clock cycle??  That is, what's the ratio [(cycle time)/(gate delay)]?
 
Presuming for the moment that Cray & Thornton's "CDC-6600" machine was
well-designed :-), its figure of merit is 20 gate delays per clock cycle. **

Of course, wiring delay due to the speed-of-EMwaves is detrimental.  So
the ratio of cycle time to gate delay gives an optimistic number for
how many gates the longest path can _really_ contain; unless the machine is
teeny tiny with negligible wiring delay.

What is the gate-delays-per-clock-cycle number for other computers?  Does
anybody know, for example,
	ETA-10?
	Amdahl 580?
	IBM 801 (risc minicomputer)?
	Cray Research Y-MP?
	IBM 360/91?

Pedagogical question: is there a "correct value" for gate delays per clock
cycle that represents a good tradeoff, empirically determined over the
last 30 years, that's best in fast machines?
 
aside remark:
Browsing through my e-mail archives today, I came upon an old message
from 1988 that purported to describe the (at the time, hypothetical)
Cray-3.  A pair of listings leaped off the screen and really astonished me:

	Instruction issue rate:			1 new instruction per cycle
	# of gate delays per clock cycle:	6 gate delays per cycle
                                               ^^^
_________ WOW !! _______________________________|


** The 6600 used a really wacko design for (clock pulses + latch schematic)
   resulting, apparently, in a setup time of 5 gate delays!!  {25ns out
   of 100ns according to Thornton's book}.  So the logic seems to have
   only had 15 gate delays to calculate results.

-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}