Article View: comp.arch
Article #2789Re: Gate delays in fast computers
From: Ashok Singhal
Date: Mon, 23 Oct 1989 19:39
Date: Mon, 23 Oct 1989 19:39
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In article <29862@obiwan.mips.COM>, mark@mips.COM (Mark G. Johnson) writes: > Path: pasteur!ucbvax!tut.cis.ohio-state.edu!gem.mps.ohio-state.edu!apple!mips!mark > From: mark@mips.COM (Mark G. Johnson) > Newsgroups: comp.arch > Subject: Gate delays in fast computers > Message-ID: <29862@obiwan.mips.COM> > Date: 21 Oct 89 22:13:42 GMT > Lines: 45 > > > > For a "well designed" computer, how many gate delays are there in one > clock cycle?? That is, what's the ratio [(cycle time)/(gate delay)]? > Here is a reference that answers your question: Steven R. Kunkel and James E. Smith, "Optimal Pipelining in Supercomputers", Proc. 13th Annual Symposium on Computer Arechitecture, June 1986. The paper discusses your question in detail, including an analytical formulation of the problem and uses simulation to get numbers for a few programs for a Cray-1S. They conclude that 8-10 gates per pipeline segment is optimal. Well written paper. Ashok
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!cs.utexas.edu!tut.cis.ohio-state.edu!ucbvax!pasteur!proxima.Berkeley.EDU!Singhal From: Singhal@proxima.Berkeley.EDU (Ashok Singhal) Newsgroups: comp.arch Subject: Re: Gate delays in fast computers Message-ID: <18704@pasteur.Berkeley.EDU> Date: 23 Oct 89 19:39:14 GMT References: <29862@obiwan.mips.COM> Sender: news@pasteur.Berkeley.EDU Lines: 29