🚀 go-pugleaf

(sci.electronics added to newsgroups -- seems apt)

In article <1989Oct19.163734.20976@utzoo.uucp> I wrote:
>>> (One of the gems of my collection is an unintentionally-hilarious paper
>>> from an IEEE conference proceedings that proves, in some detail, that it
>>> is impossible to build 64Kb DRAMs with optical lithography.)
>>
>>O.K., now please tell us which limiting assumption went wrong and why.
>
>Hey, I'm a systems programmer, not a chip designer -- *I* don't know! :-)

Several people have expressed interest in this goodie, so herewith some
details.  The paper is from IEEE Compcon Spring 1977, titled "Prospects
for the 64K RAM - an outline of the problem", by Paul R. Schroeder of
Mostek.

He first observes that as of the then-current state of the art (16K RAMs),
a significant fraction of the increase in density came from simpler cells,
but this has effectively hit a dead end with the one-transistor one-capacitor
cell.  "Multiple bit/cell RAM storage is, unfortunately, out of the question."

He shows a typical layout of a bit cell in a 16K RAM.  "...diffused digit
sense lines, a metal word line, and one metal to (2nd level) polysilicon
contact per two cells".  "Other configurations are possible - for example,
by utilizing polysilicon word lines and metal digit lines - however these
generally require tighter design-rule tolerances to achieve the same cell
area."  "...the vertical cell dimension is determined by metal, which is
design-rule limited and completely dense.  In the horizontal direction the
cell dimension is the sum of the digit diffusion width, cell pass-transistor
channel length, one dimension of the storage capacitor, and one channel-to-N
isolation spacing... utilization of silicon area is actually very efficient.
...reduction in area of this cell (without tightening design rules)... must
apparently reduce cell width by this amount.  Attempts along this line have
been made but do not seem destined for instant success."

He goes on to comment that current sense-amplifier designs require width
about equal to the then-current cell width anyway, as do column decoders.
"...it seems that we are stuck with essentially the present cell area...
invention of a rather high order is required [for improvement]."

He then considers a brute-force approach.  "...split array of double-poly
memory cells with dynamic flip-flop sense amplifiers as in present 16K...
no increase in the number of cells per sense amplifier beyond 128 (as used
in present 16Ks) is feasible, since the attendant increase in digit-line
capacitance would reduce the read-out signal below detectable levels...
already in the 100 mV range in the present 16K...  the most efficient column
decoder architecture [puts them in the center] with sense amplifiers...  Row
decoders can, however, be shared..."  The resulting design is a vertical bar
of input buffers and row decoders, six horizontal strips (#2 and #5 being
sense amps and column decode, the others memory), and another vertical bar
of clock generators and control.  "Dimensions of such a chip using present
16K RAM layout rules would be approximately 0.230x0.385.  With a die area
of nearly 90,000mil^2 and present state-of-the-art wafer processing...
high-volume manufacture is not commercially feasible... active power
dissipation on the order of 0.8W...  magnitude of current transients...
in a [full-chip] refresh cycle... very likely unacceptable...  a 16-pin
DIP could not accommodate such a large die."

His conclusion is that 64Kb RAMs will experience long development delays,
and a 32Kb RAM is probably viable as an intermediate stage.

Commercial 64Kb RAMs were announced at about the same time as the paper
was published, and were available a few months later.
-- 
A bit of tolerance is worth a  |     Henry Spencer at U of Toronto Zoology
megabyte of flaming.           | uunet!attcan!utzoo!henry henry@zoo.toronto.edu