🚀 go-pugleaf

In article <20764@usc.edu> vorbrueg@bufo.usc.edu (Jan Vorbrueggen) writes:
>In article <36597@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov (Eugene Brooks) writes:
>
>>Given equivalent performance interconnect, which rarely occurs because the
>>message passing machines tend to get short changed on the comm. hardware,
>>I have found the "shared memory" systems to have much better communication
>>performance ...

>Eugene, ever seen a transputer? Overhead for receiving or sending a 
>message is 19 cycles (630 ns for a 30 MHz part). The actual transfer
>is done by a dedicated DMA machine at a maximum rate of 1.7 Mbyte/s
>unidirectional or 2.4 MByte/s bidirectional.

1) Although it has high? peak bandwidth, the latency is still there.
The interconnect system waits for the processor to do an access, then
the processor waits for the interconnect to get the data.  Many
microseconds go by between the time the CPU needs dependent data and
it is usable.

2) This thread has been leaning toward the 'many killer micros in
parallel' being the supercomputers of the future.  I agree, but I
think it is still far away; commodity micros just don't include what
they need to support massively parallel systems, in the sense of
providing ease-of-use in a general purpose way.  And they never will,
if the #1 priority is to run whetstone and dhrystone fast.  Providing
these capabilities requires assumptions all the way from application
development, through the compiler, the OS, the chip interface, and on
down to the bare silicon.  It is Real Tough for the guys who design
commodity chips to anticipate what the vast range of users are going
to want, and they're just going to end up not pleasing everybody.

Please recall that even the hypercubes (well inmos, ncube and thinking
machines anyway) do not use commodity microprocessors, but proprietary
ones that do the extras in hardware that they need 

-Stan    Disclaimer: not necessarily the views of my organization.