🚀 go-pugleaf

In article <3300080@m.cs.uiuc.edu> gillies@m.cs.uiuc.edu writes:
  >
  >At some point I heard that MIPS pulled out just about every stopper to
  >speed up the floating point speed of the R2000/R3000.  In other words,
  >they hardwired all the FPU ops, and provided 32 or 64-bit circuitry
  >wherever it was needed, and used all the optimal designs (like carry
  >lookahead and wallace trees -- please excuse my ignorance of
  >arithmetic circuitry) in their arithmetic unit?
  >
  >So now they just wait for device technology and heavy pipelining to
  >speed up their chip?  Couldn't Crays make a small comeback by
  >exploiting their 1's complement arithmetic, which is supposed to be an
  >inherently faster number system for digital implementation?

MIPS chose the IEEE-754 standard for floating point representation and
arithmetic; the other candidates were perceived to be marketing suicide.

The FP device is indeed hardwired (i.e. no microcode) and it has
several different functional units so that four different FP operations
can be executing in parallel ("overlapped"): an FP load/store, an FP
add/subtract, an FP multiply, and an FP divide.  {It's described in
IEEE Micro, June 88}

However, the chip contains only 75,000 transistors.  So there were
lots of potentially nifty hardware ideas that had to be omitted from
the design, to stay within budget.

Specifically, there are no Wallace trees in the R3010.  The carry
circuits on the R3010 are not the classical "lookahead" variety.
The register file only has 4 ports.  Etc etc etc.

Of course, now that it is possible to cram a lot more than 75,000
transistors on a chip, perhaps it's reasonable to postulate that the
additional transistors could be used to improve f.p. performance.
(On top of speedups due to faster technology)
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}