🚀 go-pugleaf

In article <224@dg.dg.com> uunet!dg!daver (David Rudolph) writes:
>In article <36662@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov (Eugene Brooks) writes:
>>In article <20764@usc.edu> vorbrueg@bufo.usc.edu (Jan Vorbrueggen) writes:
>>>Message forwarding isn't so difficult either. I've read of a system
>>>requiring less than 10 us overhead per through-route
>>This level of overhead for each hop is completely intolerable.

>And what is the overhead for each interconnect level in a "shared
>memory" machine such as the ultracomputer?  Keep in mind that in such a
>machine, every non-local memory access must go through each level and 
>back while the processor waits.

How does two clock ticks per node sound? One for routing and one on
the wires. If you processor is slow enough it might be only one :-)

Your second statement has two false assumptions in it. First, no need
to build a "dancehall" machine: embed the processors in a 3d mesh so
that each processor is closer to some memory than the rest. Say 256
processors in a 16x16x16 cube gives an average distance of 12 hops to
a memory module. Note that this is half again log(256)=8 but there are
packing issues, message flux issues, and redundant path issues that
make the comparison difficult.

The second false assumption is that the processor waits. Sure, with
memory 50 cycles away its easy to build a machine that waits but it is
also possible to build a machine that multiplexs 50 independent
instruction streams on one ALU so, with sufficient parallelism the
memory latency is a non-issue such as the HEP. Of course, you need 50
streams.

-- 
David Callahan  (david@tera.com, david@june.cs.washington.edu,david@rice.edu)
Tera Computer Co. 	400 North 34th Street  		Seattle WA, 98103