🚀 go-pugleaf

[I had complained about the hype saying "America" would run at 5
instructions per cycle.]

billms@dip.eecs.umich.edu (Bill Mangione-Smith) writes:
> In all of the writings I have seen, including the iccd paper, the stated
> performance goal is something just over 1 instruction issued per clock...

OK, fine.  I haven't seen the paper(s).  What I was complaining about was
the hype surrounding it, NOT the technical characteristics of the processor
itself.  I'll give a couple of examples from 10/9 _EE_Times_ since that's
the one I have handy right now:

	"In technical papers presented at the International Conference on
	Computer Design, IBM claimed peak operation of five instructions
	per cycle..."

Note the wording.  Somehow, somewhere along the way, I suspect that a
technical statement--that it is possible to issue five instructions in one
cycle--got turned into "peak operation" with a rate.

> ...IBM, atleast the R&D types, doesn't seem to be
> trying to fool anyone that the actual performance is anywhere near
> 4 or 5 instructions per clock...
>...Have you been talking to sales guys?...
[see the original posting--I said I was talking about the trade press]

Here's another one, and again you have to think carefully about the
wording:
	"Randy D. Groves, manager of RISC workstations at the Austin
	Advanced Workstation division...[said]...`While both Apollo's Prism
	and Intel's i860 had the same second-generation RISC goals--com-
	pound function instructions and a superscalar machine with more
	than one instruction per cycle--we actually met our goal of
	executing four, and with the compound accumulate instruction, five
	instructions simultaneously, in one cycle,'..."

This statement leads you right to the edge of the idea of a rate of five
instructions per cycle, if you're thinking carelessly.  But there's no real
connection made between the possibility of issuing five instructions in a
cycle (an event) and what any believable rate (series of events over time)
might be.  The trade press is more than happy to supply that nonexistent
connection.

Again, I am NOT flaming the processor design.  Yes, you need to issue
multiple instructions per cycle if you're going to beat the 1 CPI
goal--that's "obvious".  What I'm after is that we (or at least I, so far)
haven't seen any realistic figure for instruction issue rate, yet I keep
seeing this magic "5" thrown around.  People should be saying there are 5
(or maybe 4, accounting for multiply/accumulate) independent functional
units which can execute instructions, and get rid of this "5 instructions/
cycle" crap.
-- 
Dick Dunn     rcd@ico.isc.com    uucp: {ncar,nbires}!ico!rcd     (303)449-2870
   ...Worst-case analysis must never begin with "No one would ever want..."