🚀 go-pugleaf

In article <863@metaphor.Metaphor.COM> philf@xymox.metaphor.com (Phil Fernandez) writes:
>In article <1989Oct27.050923.5294@ico.isc.com> rcd@ico.isc.com (Dick Dunn) writes:
>>... The
>>processor may be able to issue 5 instructions in some ideal cycle, but it
>>does NOT run at 5 instructions/cycle for any believable piece of code!
> 
>At an all-day IBM briefing last August on the new machine
>architecture, the IBM folks tole me over and over, "5
>instructions/cycle".  As this went on, I became increasingly skeptical
>and inquisitive, and finally pushed the issue.  In the end, IBM
>admitted that in real-world situations, they saw more like 1.0-1.2
>instructions/cycle. 5i/c is just a theoretical maximum.  Don't believe
>the hype, boys and girls...
>
>pmf
>
>(This opinions are mine only, and do not reflect the opinions of Metaphor)
>

Please excuse me if you have heard it here before, but the
Trace Scheduling Compacting Compiler(TM) here at Multiflow
Computer frequently schedules 10 or more of maximal 14
available instructions on our TRACE 14/300 Compiler.  Is it
easy? No.  Would you want to write code like this by hand? No.
Can I produce a pathology in which only sequential code is
generated?  Of course I can.

But the compiler technology exists today to find the inherent
low level (fine grained) parallelism in lots of real-world
situations.  As dramatic improvement in cycle time become more
difficult to produce, it is the compiler generated
parallelization of code that will ultimately produce minimal
time to solution.

(Usual disclaimer about source of opinions).
			Marshall Presser
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