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Article #2939

Re: RISC vs CISC (rational discussion..) + new IBM 'beyond RISC'

#2939
From: Gerry Gleason
Date: Fri, 10 Nov 1989 20:13
39 lines
2699 bytes
In article <36340@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:
>[]
>>In article <31031@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>>ARGUMENT 4: RISC is better, because it's simpler, and hence there is faster
>>	time to design and test the chips.
>>	COMMENT: maybe, maybe not.
>   Agreed. Notice as we get more and more transistors, we start to do more
>   complex (superscalar, hi-perf FP, graphics) things, not just add more
>   cache.  Superscalar may double your performance. It would literally
>   impossible to add enough cache to do that, so simple, regular hardware is
>   probably not where the transistors will go. (for disbelievers, if your
>   cache miss penalty * miss ratio <1, then even if every access hits, you'll
>   save less than a cycle, so CPI approaches 1. Superscalar does better.)

I think part of the problem is that not everyone means the same thing by
RISC.  As I said in an earlier posting, it's not RISC vs CISC, but simply
apply the KISS principle to every aspect of design, or maybe more to the
point, before you put in a feature you had better be sure it is a big win.
Small wins are not worth the headaches that the complexity brings.  In fact,
if you can throw out a large chunk of complexity (from the instruction set
or addressing modes for example), you will have capacity for more hot-rod
features (i.e. pipelines, and some of the things you mentioned).

Another aspect of RISC is that it is a move to more modular, less ad-hoc
architectures.  The architects that are pressing the RISC debate are
applying the same ideas that help software engineers deal with million
line programs to help hardware engineers deal with million transistor
chips.  The issues are the same.

Gerry Gleason

My cohorts here at Zenith think I need a disclaimer to say this is my
opinion and not Zenith's.  IMHO, anyone who assumes a posting to the
net represents the organization they work for is nuts.  I know it happens,
but how often is the posters opinion even represented.  So I will just
waist net bandwith this once with a disclaimer:

	"No complany will let me speak for them anyway, and
	 I reserve the right to change my opinion without notice"
Technical Details
Message-ID: <14@zds-ux.UUCP>
Path: arc1-ca.pugleaf.net!utzoo!utgpu!utstat!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!zds-ux!gerry
References: <503@ctycal.UUCP> <31031@winchester.mips.COM> <36340@apple.Apple.COM>

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!utstat!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!zds-ux!gerry
From: gerry@zds-ux.UUCP (Gerry Gleason)
Newsgroups: comp.arch
Subject: Re: RISC vs CISC (rational discussion..) + new IBM 'beyond RISC'
Message-ID: <14@zds-ux.UUCP>
Date: 10 Nov 89 20:13:12 GMT
References: <503@ctycal.UUCP> <31031@winchester.mips.COM> <36340@apple.Apple.COM>
Reply-To: gerry@zds-ux.UUCP (Gerry Gleason)
Organization: Zenith Data Systems
Lines: 39