🚀 go-pugleaf

In article <36340@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:
$>In article <31031@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
$>ARGUMENT 2: RISC is better for cost reasons, because it's smaller
$   When you get to 1M transistors on a chip, the space for some extra decoding
$   logic is neglible. This argument works only during the initial (e.g.
$   'new technology' phase.

$>ARGUMENT 3: RISC is better, because even if there is enough space on a die
$>	to put a whole CPU plus other things, the RISC can afford more space
$>	for caches and other good things, and so it will be faster.
$    See argument above. What is the performance difference between a 32k cache
$    and a 31k cache?

   I have beside me an article stating that on the Berkeley RISC I and II chips,
between 6 and 10 percent of the chip area was used for decoding and control
logic.  Compare this with a figure of 50-60% on a 68000 or Z8000 ... now, I
must admit that I've never designed an on-chip cache for a RISC chip, but
somehow I think it would be quite easy to get more than a 1k cache out of
40-54% of the chip size.  After all, if each 1k of cache size takes even 40%
of the chip's area, how would you get a 32k (or, for that matter, 31k) cache
on a chip in the first place?
-- 
Stephen M. Dunn                               cs4g6ag@maccs.dcss.mcmaster.ca
          <std_disclaimer.h> = "\nI'm only an undergraduate!!!\n";
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