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Article #2973Re: RISC multiprocessors
From: Michael Z Slater
Date: Sun, 12 Nov 1989 18:10
Date: Sun, 12 Nov 1989 18:10
12 lines
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1054 bytes
>The R3000 (mips) has support for necessary multiprocessing features >built in. There is support for reading from the data cache and invalidating >data cache entries. This would allow a snooping system to be built fairly >efficiently. Snooping directly on the primary R3000 cache is indeed possible, but as I understand it, the degradation on CPU performance due to contention for the cache is signficant. Plus, the R3000 cache is write-through, and a reasonable multiprocessor system needs write-back caches. All multiprocessor R3000 system I'm aware of use second-level write-back caches. Michael Slater, Microprocessor Report mslater@cup.portal.com
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!portal!cup.portal.com!mslater From: mslater@cup.portal.com (Michael Z Slater) Newsgroups: comp.arch Subject: Re: RISC multiprocessors Message-ID: <23963@cup.portal.com> Date: 12 Nov 89 18:10:05 GMT References: <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM> Organization: The Portal System (TM) Lines: 12