🚀 go-pugleaf

I can think of two methods of supporting cache coherence for multi level
caches. These all assume that there is a first level internal cache w/ a
some method of invalidating (or flushing) a line and a second level cache
connected to the bus.

The easy method is to use write through cacheing for both levels. Every
time a write occurs on the system bus flush the address from both caches.
This has performance penalties because typically every invalidate cycle on
the internal cache blocks the execution unit from access it.

A second harder method is to keep the internal cache a subset of the
external cache. Every time a line is removed from the external cache
invalidate that line in the internal cache. All system bus access are
looked up in the second level cache directory. Only those access that are
contained in the external cache are invalidated from the internal cache so
there is less contention for the internal cache.

The second method could be expanded to keep track of whats in the internal
cache in the external directory so only lines in the internal cache are
invalidated. Problem with this is knowing whats in the internal directory.
You don't see all the processor access so if your using a LRU type
replacement strategy you have no idea outside the chip what's going to be
replaced in the internal cache. If the internal cache always signaled the
outside cache on replacements, the ouside cache would know and could filter
the invalidate traffic.

You can layer a writeback external cache on this protocal and even layer a
internal writeback cache.

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Tom Shott    INTeL, 2111 NE 25th Ave., Hillsboro, OR 97123, (503) 696-4520
	     toms@omews44.intel.com OR toms%omews44.intel.com@csnet.relay.com
	INTeL.. Designers of the 960 Superscalar uP and other uP's