🚀 go-pugleaf

In article <3024@brazos.Rice.edu> preston@titan.rice.edu (Preston Briggs) writes:
>In article <22303@gryphon.COM> scarter@gryphon.COM (Scott Carter) writes:
>
>>ISSUE one instruction per cycle.  The 960 CA can issue three instructions per
>>cycle to the chosen three of four execute units.  I believe Intel has figures
>>showing that on the average they could infact issue two instructions per clock
>>_average_ [over what program set?], hence the 960CA can legitimately be called
>>66 Native MIPS average with 99 Native MIPS peak.  

As hawkes said, MIPSco uses a rating system that tries to approximate
performance versus a VAX-11/780 with good compilers on a mixture of
large program that do include both integer and floating-point computations.
Peak native instruction rates have NOTHING to do with such ratings,
i.e., they tell you nothing about the speed of chips in systems running
real programs.  Only benchmarks of real programs on real machines do that...

>I think that's too optimistic.
>We've played some with an i860 on an evaluation board.
>The supplied compilers didn't attempt to issue more than 
>1 instruction/cycle (out of a max of three).  

Note: I think this statement is offering data (thanx!) on a related issue,
and did not confuse the two chips, but just to make sure,
i860s and i960s are completely different chips.

To answer the question that started this all, the R6000 and i960 are
about as far apart in usage as one can imagine.  The i960 is clearly
targeted at embedded control, and the i960CA has neither FPU nor MMU
(which is perfectly OK), hence it is unlikely that you'll see it running the
SPEC benchmarks any time soon.....   One of the topics of discussion
at the Microprocessor Forum was that the benchmark confusion in the
embedded side of the world is even worse than in the systems side...
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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