🚀 go-pugleaf

In article <3044@brazos.Rice.edu> preston@titan.rice.edu (Preston Briggs) writes:

>Right.  I was just trying to cast aspersions on data that suggest we're
>going to see an average of 2 instructions/cycle sometime this decade
>(wow, big claim).  It might be a couple of years.  
>The problem is lack of compilers, not the chips.

>On the other hand, Multiflow has probably been doing it for years.

Actually, the Multiflow is a positive example of designing hardware and
software together and making the tradeoffs in hardware according to
what compilers might ACTUALLY do, not what hand-written code can do.

One cannot just blame the compilers for not taking advantage of all of
the features, especially if compiler writers were not heavily
involved in the design.  Some readers may recall the last session at
the Hot Chips conference, in which some experienced compiler writers
bemoaned the berserkery of some chip designs, and the general lag of
compilers behind chip designs.  I especially liked Steve Johnson's
discussion of how compiler writers, even if asked about chip design
(usually aren't) seldom have enough time to help it because they're
frenziedly trying to catch up with the previous thing.  He showed a nice
hunk of pseudo-code:
	
"CRISIS -- COMPILERS LAG HARDWARE
	repeat
	{
	Compiler writers work on last generation
	Chip dsigners design next generation
	THUS: next chips hard to compile for
	} until ( we wise up ) "

Now of course, it may well be that in RESEARCH projects, one is exploring
what can be done, and trying to understand the implications, and this may
lead to designs that stretch compilers heavily [presumably done as part
of same project :-)].  but it is amazing to see people doing this for
things expected to be commercial, reprogrammable products....
Of course, everything said for compiler writers goes for operating
systems folks as well, at least.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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