🚀 go-pugleaf

In article <31547@hal.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>In article <7000@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
>  >CMOS isn't like that. It's asymmetric, and cares about transitions:
>  >0=  >1 takes more power than 1=  >1. So, one can write worst-case
>  >programs, which generate on-chip noise (mass transitions on the wide
>  >datapath), or which generate board noise and heat (mass transitions
>  >on the address and data pins). I'm not sure what cache activity
>  >generally produces the most heat: it may depend on implementation.

>It's a terrible shame that CMOS parts are being shipped to customers,
>for money, which operate over 50MHz.  The ECL/GaAs/BiCMOS folks have
>apparently discovered reasons why it can't be done.

>Perhaps Brooktree ought to initiate a recall of their CMOS devices
>"Bt458" and "Bt468", which operate at 170 and 200 MHz respectively.

> etc etc

The article didn't say "CMOS faster than 50MHz can't be done."  The issue
is not designing chips.  The issue is putting them in a system and trying
to get them to work.

Just a few of the many system problems CMOS has that ECL doesn't have:

The fast CMOS has such fast rise times that we EE's need to become
physicists in order to design transmission lines good enough to 
maintian signal integrity, without slowing signals down so much you
might as well use TTL.

The fast CMOS has such fast rise times that ground bounce causes chips
to malfunction.

The fast CMOS often does not have enough DC drive to allow proper line
termination.

I'm not saying it can't be done; but it isn't for the faint of heart, 
let me tell you.

The CMOS guys have a ways to go before they catch up to where the ECL
guys are, in designing for highly reliable, high speed, system level
interconnectivity.
-Stan