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Article #3056Re: What CMOS cannot do (Re: Surges)
From: Donald Lindsay
Date: Sat, 18 Nov 1989 22:29
Date: Sat, 18 Nov 1989 22:29
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In article <48393@bbn.COM> slackey@BBN.COM (Stan Lackey) writes: >The CMOS guys have a ways to go before they catch up to where the ECL >guys are, in designing for highly reliable, high speed, system level >interconnectivity. Obviously, high-end ECL systems have workable answers: they're pretty reliable. How about the new ECL from BIT, namely their SPARC and MIPS R6000? I haven't seen details yet, but I assume that there weren't enough pins to use a complementary pair for each IO. And when do we see a BiCMOS micro, with a CMOS core and ECL IO? Or will the core go BiCMOS too, to avoid all the di/dt issues that the ECL people are so quick to point out? -- Don D.C.Lindsay Carnegie Mellon Computer Science
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Path: arc1-ca.pugleaf.net!utzoo!yunexus!ists!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!pt.cs.cmu.edu!MATHOM.GANDALF.CS.CMU.EDU!lindsay From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) Newsgroups: comp.arch Subject: Re: What CMOS cannot do (Re: Surges) Message-ID: <7032@pt.cs.cmu.edu> Date: 18 Nov 89 22:29:49 GMT Article-I.D.: pt.7032 References: <7000@pt.cs.cmu.edu> <31547@hal.mips.COM> <48393@bbn.COM> Organization: Carnegie-Mellon University, CS/RI Lines: 15