Article View: comp.arch
Article #3120Re: High speed bus on the new MIPS R6000 box
From: David Collier-Brown
Date: Thu, 23 Nov 1989 14:45
Date: Thu, 23 Nov 1989 14:45
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1337 bytes
ruiu@dragos.uucp (dragos) writes:
[about bus speeds]
>As well, what kind of memory designs can steadily deliver hundreds of MB/sec. ?
>We were told that the MIPS box has 594K of cache (67Mhz, hmmm... 20ns I assume)
>so maybe all reads and writes are page mode and each memory board has
>a cache too ?
I don't know about modern stuff, but my old HoneyBun[1] used to fetch
eight 72-bit+ecc double-words at a time from several (I think 4) physical
boards. This gave lots of bandwidth, with the usual problems of latency.
The bus wasn't (well, it was about 4" of dedicated wire), so it could
happily run fast.
--dave (history is fun: so is monomania) c-b
[1] a Honeywell, now Bull, three-processor DPS-8/70M
--
David Collier-Brown, | davecb@yunexus, ...!yunexus!davecb or
72 Abitibi Ave., | {toronto area...}lethe!dave
Willowdale, Ontario, | Joyce C-B:
CANADA. 416-223-8968 | He's so smart he's dumb.
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!ists!yunexus!davecb From: davecb@yunexus.UUCP (David Collier-Brown) Newsgroups: comp.arch Subject: Re: High speed bus on the new MIPS R6000 box Keywords: R6000 MIPS bus bandwidth Message-ID: <5384@yunexus.UUCP> Date: 23 Nov 89 14:45:48 GMT References: <1989Nov21.032355.5779@dragos.uucp> Organization: York U. Computing Services Lines: 20