🚀 go-pugleaf

Dragos Ruiu asks the following questions about the MIPS ECL system:
>In the box, the chip runs at 67Mhz, and the backplane runs at 270MB/sec.
>The bus is 32 bits wide, and 270Mb (255.6 actually) is needed to supply
>one piece of data on every clock cycle. The question that comes to mind
>immediately: How many hoops did the designers have to jump through to
>achieve this ? Does anyone have any information on just how difficult
>it is to do a design at this speed ? (I'm told by those who have done it
>that even working at 40MHz is a pain because of capacitance problems.)
>Are bus connectors a problem at high speeds ? 
>
>This 270MB/sec. figure was surprising to me - previous high speed busses I
>had seen were in the range of 80-128 MB/sec. Am I just behind the times ?

Unlike all standard buses I'm aware of, the MIPS system bus uses ECL levels,
with a differential pair for each signal.  The bandwidth is simply derived by
one transfer per clock times four bytes per transfer.  To help make long
bursts practical, the R6020 bus interface chip includes a two 36-entry
FIFOs.

The capacitance problems at 40 MHz you refer to are very real, but are
due to the use of CMOS drivers and CMOS voltage levels.  Having bipolar
drivers and ECL levels makes things much easier at high clock rates.
One tradeoff, of course, is power. The R6000 spec projects 12-15 watts
worst case at 80 MHz, but specs supply current at 4 amps max.  That's just
the CPU chip!  Add the FPC, FP multiplier, cache rams, and a bunch of
gate arrays and PALs, and you have a small room heater.

Note that this is not a general-purpose I/O bus; the MIPS system also has
multiple VME buses for I/O.

>As well, what kind of memory designs can steadily deliver hundreds of MB/sec. 
>We were told that the MIPS box has 594K of cache (67Mhz, hmmm... 20ns I assume
>so maybe all reads and writes are page mode and each memory board has
>a cache too ?

The cache is two-level, with 8 ns RAMs for the first level (16K data and
64K instruction) and 15 ns for the second level (512K combined I+D).
I assume that virtually all bus transactions are bursts, and that page mode
is used on the memory boards. 

>I wonder how much cache misses cost at 67MHz. I wonder how often they happen
>in the MIPS design.

Miss cost is about 65 clock cycles (!).  MIPS literature say that "observed
hit rate on a wide range of programs is 99.5 percent."

Michael Slater, Microprocessor Report    mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto, CA 94306
415/494-2677   fax: 415/494-3718
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