🚀 go-pugleaf

In article <3899@scolex.sco.COM>, seanf@sco.COM (Sean Fagan) writes:
> Well, NeXT *does* have the right idea, almost.  They have chips to offload
> some of the work from the CPU (the DSP and the I/O controllers).  However,
> the bus doesn't seem to allow the DMA to happen at the same time the CPU
> wants memory.  That is, somebody loses cycles.  It might be possible to get
> around this, but I don't know enough about the machine to speculate too much
> (anybody from NeXT reading this?).

To get around the problem you really have to have more than one bus -- the
old "can't have two things at the same place at the same time" problem.

Some of the high end PCs have multiple busses along the lines of the DEC minis.
That is, they have a CPU and local memory bus, and an external memory and I/O
bus.  They usually lock the high speed bus when the I/O bus is active, though,
so it really just allows you to have memory faster than the I/O bus would
allow (the whole point, originally).

The point of this posting is that this is really what makes a mainframe: so if
we put a micro togather with 4 486s (or 4 SPARCs) and 10 186s each controlling
an AT bus running independently of each other, each processor having 13 high-
speed channels to communicate with the other 13 processors, the box would REALLY
have all the performance (if it were well designed) as a comparable mainframe.

And it might be as big as one, and it might be as expensive as one.  In fact,
I get the feeling that something like this is what the next generation mainframe
computers will be.

> Sean Eric Fagan  | "Time has little to do with infinity and jelly donuts."
> seanf@sco.COM    |    -- Thomas Magnum (Tom Selleck), _Magnum, P.I._
> (408) 458-1422   | Any opinions expressed are my own, not my employers'.

Charles Marslett
chasm@attctc.dallas.tx.us