Article View: comp.arch
Article #3309Re: Intel 860 Architecture
From: Mark G. Johnson
Date: Sun, 10 Dec 1989 16:25
Date: Sun, 10 Dec 1989 16:25
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1442 bytes
Two ">>" for hamrick@convex.COM (Ed Hamrick);
One ">" for ccplumb@rose.waterloo.edu (Colin Plumb);
>>All in all, it looks like a well thought out chip, with a lot of clever
>>architectural trade-offs to get everything on one chip.
>
>To be honest, I wasn't too impressed when I saw it. Lots of wierd
>non-orthogonalities and I still think the interrupt handling is
>a pig. But I believe some of the design team reads comp.arch; let
>them refute.
I'd suggest that the Solborne/Mitsubishi _Million_Transistor_SPARC_ chip
(having CPU, caches, and floating point on one die, very much like the 860)
is a lot better thought out, with lots more architectural cleverness.
Including the idea that the computer needs to run an operating system
efficiently, and that user programs written in high-level languages
should run quickly.
--
-- Mark Johnson
MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
(408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}
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arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!tut.cis.ohio-state.edu!cs.utexas.edu!usc!jarthur!bridge2!mips!markReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!tut.cis.ohio-state.edu!cs.utexas.edu!usc!jarthur!bridge2!mips!mark From: mark@mips.COM (Mark G. Johnson) Newsgroups: comp.arch Subject: Re: Intel 860 Architecture Message-ID: <33258@hal.mips.COM> Date: 10 Dec 89 16:25:37 GMT References: <3818@convex.UUCP> <19151@watdragon.waterloo.edu> Reply-To: mark@mips.COM (Mark G. Johnson) Organization: MIPS Computer Systems, Inc. Lines: 21