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Article #3333Re: Cyrix - Fast Divide, etc.
From: michael k finegan
Date: Wed, 13 Dec 1989 17:18
Date: Wed, 13 Dec 1989 17:18
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davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) writes: >In article <112400012@uxa.cso.uiuc.edu> afgg6490@uxa.cso.uiuc.edu writes: >| >| comp.arch might be interested in a few details about the >| Cyrix math chip. This is a 387 / Weitek compatible chip, >| boasting significant speedups. (Biggest speedup, of course, >| is avoiding the coprocessor interface). > Two questions: (1) since this is a plug-in replacement for the 80387, >how does it avoid the coprocessor interface, ~ ~ ~ >-- >bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) According to the technical support group at Cyrix, there is a "memory mode" where the Cyrix chip interprets the instruction stream, and decodes 80x87 opcodes without 80x86 intervention. This has been demo'ed, and requires extra hardware (i.e. plug in board ?). Apparently this arrangement yields the full 5.5 Mflop performance; the 33MHz (etc.) 80386 SLOWS DOWN the Cyrix chip :-). I have looked at the manual for the chip - it looks like it duplicates the 80x87 only - not Weitek. Mike Finegan mfinegan@uceng.UC.EDU
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arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!purdue!iuvax!uceng!mfineganReferences:
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!purdue!iuvax!uceng!mfinegan From: mfinegan@uceng.UC.EDU (michael k finegan) Newsgroups: comp.arch Subject: Re: Cyrix - Fast Divide, etc. Message-ID: <3134@uceng.UC.EDU> Date: 13 Dec 89 17:18:56 GMT References: <112400012@uxa.cso.uiuc.edu> <1904@crdos1.crd.ge.COM> Organization: Univ. of Cincinnati, College of Engg. Lines: 27