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Article #3447Re: Cool CMOS at ECL speeds (?)
From: gillies
Date: Thu, 18 Jan 1990 02:46
Date: Thu, 18 Jan 1990 02:46
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1306 bytes
This is very interesting. Perhaps someone should write a "meltdown"
benchmark to test CMOS microprocessors. The program counter should
continually oscillate between two complementary binary numbers. All
registers should be complemented as often as possible. On the i860,
all 3 dispatched instructions should cause complementation on every
cycle. If you knew the internal architecture, I'm sure you could
torture other registers too. Maybe block-load all the registers with
-1 and then execute an instruction to zero all registers at once. I
wonder how much of a power transient is possible on a CMOS
microprocessor.....
Don Gillies, Dept. of Computer Science, University of Illinois
1304 W. Springfield, Urbana, Ill 61801
ARPA: gillies@cs.uiuc.edu UUCP: {uunet,harvard}!uiucdcs!gillies
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!uakari.primate.wisc.edu!brutus.cs.uiuc.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!m.cs.uiuc.edu!p.cs.uiuc.edu!gillies From: gillies@p.cs.uiuc.edu Newsgroups: comp.arch Subject: Re: Cool CMOS at ECL speeds (?) Message-ID: <76700117@p.cs.uiuc.edu> Date: 18 Jan 90 02:46:00 GMT References: <50985@bbn.COM> Lines: 15 Nf-ID: #R:bbn.COM:50985:p.cs.uiuc.edu:76700117:000:801 Nf-From: p.cs.uiuc.edu!gillies Jan 17 20:46:00 1990