Re: Dynamic internal state

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Article #3508

#3508

From: Steve Golson
Date: Thu, 15 Mar 1990 01:33

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In article <36999@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>     Motorola 68030           max clock period =   80 nanoseconds (12.5 MHz)

The on-chip caches of the 68030 (and 68020) use 4T RAM cells that must be
periodically refreshed. Anyone from Moto want to comment on what other dynamic
logic they used?

Steve Golson         sgolson@East.sun.com          golson@cup.portal.com
Trilobyte Systems -- 33 Sunset Road -- Carlisle MA 01741 -- 508/369-9669
       (consultant for, but not employed by, Sun Microsystems)
"As the people here grow colder, I turn to my computer..." -- Kate Bush

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!philmtl!philabs!gotham!east!pyrite!sgolson
From: sgolson@pyrite.East.Sun.COM (Steve Golson)
Newsgroups: comp.arch
Subject: Re: Dynamic internal state
Message-ID: <1690@east.East.Sun.COM>
Date: 15 Mar 90 01:33:25 GMT
References: <32937@shemp.CS.UCLA.EDU> <132903@sun.Eng.Sun.COM> <36999@mips.mips.COM>
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