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Article #7990MIPS and MHz
From: System Administrator
Date: Thu, 12 Nov 1992 18:34
Date: Thu, 12 Nov 1992 18:34
18 lines
988 bytes
988 bytes
I Sun has just announced some new workstations based on a microSPARC(tm) chip running at 50MHz and producing 59.1 MIPS. I know the problem with MIPS but How can a non-superscalar implementation at 50MHz run 59.1 MIPS? I thought the holy grail of RISC was 1 instruction retired per cycle and that this is never attained (much less exceeded) in a non- superscalar implementation. MIPS is probably the most misleading term in the field but what on earth can they mean? John Ahlstrom Boole & Babbage 408-524-3307 I can neither confirm nor deny that these questions are interesting to anyone else.
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Newsgroups: comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!boole!NetCmmnd From: NetCmmnd@boole.uucp (System Administrator) Subject: MIPS and MHz Message-ID: <1992Nov12.183424.29331@boole.uucp> Summary: How does a non superscalar get more than 1 instruction per cycle? Keywords: RISC, MIPS, cps Organization: Boole & Babbage, Inc. Date: Thu, 12 Nov 1992 18:34:24 GMT Lines: 18